Abstract
This paper presents a multi-mode asymmetric power amplifier (MMA-PA) with back-off efficiency enhanced. The back-off efficiency is improved without a lossy impedance inverter or signal separator which is used in conventional Doherty or outphasing amplifiers. The design considerations are provided in detail. In addition, the proposed MMA-PA operates in three different modes according to the input power level. The PA is fabricated in a 65-nm bulk CMOS technology. In the high-power (HP) mode, the MMA-PA exhibits a small-signal gain of 18.4 dB at 30 GHz and a 3-dB bandwidth of 4.5 GHz from 27.7 to 32.2 GHz. The output saturation power ( $\text{P}_{\text {sat}}$ ) and 1-dB compression power are 16.7 and 15.1 dBm, respectively. While the peak power-added efficiency (PAE) is 24.7 %, the 6-dB back-off PAE keeps a high value of 14.1 %. In the medium-power (MP) mode, $\text{P}_{\text {sat}}$ and peak PAE are 12.3 dBm and 21 %, respectively with a similar gain of 18.9 dB. In the low-power (LP) mode, the gain, $\text{P}_{\text {sat}}$ and peak PAE are 11.5 dB, 7.5 dBm and 16.5 %, respectively. With a 100-MHz 64-QAM OFDM signal following the 3GPP 5G NR standard, the average output power in the HP mode is 6 dBm with EVM of −26 dB and ACLR < −34 dBc. In the MP and LP modes, the average output power are 3.3 and 1.1 dBm, respectively with EVM of −26.6 and −26.1 dB.
Highlights
The high efficiency of power amplifiers (PAs) is significant to keep long battery time and low heat generation in transmitters
We present a multi-mode asymmetric PA (MMA-PA) which improves the back-off efficiency without using an impedance inverter or signal component separator (SCS)
An mm-wave multi-mode asymmetric power amplifier (MMA-PA) is demonstrated in a 65-nm CMOS technology
Summary
The high efficiency of power amplifiers (PAs) is significant to keep long battery time and low heat generation in transmitters. The ratio of the auxiliary transistor size to the main transistor size should be increased for a wide OBO range It should be noted from (13) that the simultaneous optimum output matching at the back-off and saturation points become more difficult with a high ISa /ISm. there is a trade-off between the OBO range and the simultaneous optimum matching in determining the asymmetric transistor size. For the simulation, both the main and auxiliary amplifiers are ideally matched to the optimum load-pull impedance at the saturation point. The loci of the load admittance seen by the main and auxiliary output transistors, Yload,m and Yload,a, respectively, are plotted as the output power varies from the saturation to back-off point. The peak PAEs in the MP and LP modes are 16 and 12.3 %, respectively
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
