An integration process of micro electro mechanical polysilicon with CMOS analog/digital circuits

Abstract

A fabrication process has been developed to integrate 2 μm-thick micro electro mechanical polycrystalline silicon (polysilicon) with CMOS analog/digital circuits. Highly conductive, stress relieved, and stress-gradient suppressed polysilicon can be integrated without significant changes in the device characteristics of MOSFETs. The thermal budget for doping and annealing the thick polysilicon is optimized in both electrical and mechanical aspects at a moderate temperature of 850°C. Mechanical and electrical properties of the polysilicon are related to the deposition temperatures, the doping and annealing conditions, and the kind of sacrificial oxide. Crystallographic properties, surface morphologies, and dopant profiles are compared. Device characteristics of n- and p-type MOSFETs fabricated in the integration process are compared with reference MOSFETs fabricated in a normal CMOS process. CMOS analog/digital circuits are also fabricated in the developed polysilicon integration process and measured.