An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS

Abstract

This article presents an interface application specific integrated circuit (ASIC) adaptable to a wide range of bio- and neuro-signal applications. The chip consists of a low-noise analogue front end (FE) and a successive-approximation analogue-to-digital converter (ADC). The entire analogue signal processing chain is fully differential for better immunity to common mode noise and interferences. To make the interface adaptable to different biopotential signals, the bandwidth and gain of the analogue FE are configurable. The ADC is designed for rail-to-rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-µm complementary metal oxide semiconductor (CMOS), input-referred noise density and more than 100-dB CMRR are obtained. Operating in a 10-bit mode, the ADC exhibits −1/+0.3-LSB DNL and −1.3/+0.8-LSB INL least significant bit integral nonlinearity for 1-V rail-to-rail input. The whole interface integrated circuit (IC) consumes 36 µW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.