An integrated CMOS mixed-mode signal processor for disk drive read channel applications

Abstract

A read channel processor architecture for Winchester disk drive applications is presented, designed to operate with data rates from 10 to 32 Mbits/sec with (1,7) Run Length Limited (RLL) encoding on a 5 volt 1-/spl mu/m CMOS technology. The processor performs the functions of pulse detection and data separation using integrated CMOS analog amplifiers and filters and a digital phase-locked loop (PLL). It integrates many of the functions previously performed with discrete components and has enhanced programmability to more fully support Zoned Bit Recording (ZBR). This paper presents an architectural overview of the processor with comparisons to existing solutions, detailing the system constraints of the architecture. Unique CMOS circuit designs are presented along with the pipelined architecture of the digital PLL.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>