An instruction systolic array implementation of the two-dimensional Fast Fourier Transform

Abstract

An Instruction Systolic Array (ISA) implementation of the two-dimensional Fast Fourier Transform (FFT) algorithm is presented in this paper. The ISA is characterised by a systolic flow of instructions instead of data as in ordinary systolic array. The ISA implementation of the two-dimensional FFT algorithm is derived following a systematic design methodology. The derived ISA for the two-dimensional FFT is modular and uses identical processing elements, with local and regular interconnections among the processing elements. For a √ N × √ N point two-dimensional FFT, the time-complexity of the proposed ISA design is O(√ fN) with N processing elements.