An Input Buffer Architecture for On-chip Routers

Abstract

The design of buffers in routers influences significantly on the area overhead, energy consumption as well as overall performance of the Network on Chip (NoC). In this paper, we propose an architecture that improves buffer utilization by using a shared buffer at each input port of the router. Because the buffer utilization is more efficient, the effect of reducing buffer size on the NoC performance can be minimized as compared to the conventional buffer architecture. We have implemented the proposed buffer architecture on Virtual Output Queuing (VOQ) router, which is a low-latency router. Simulation results show that the VOQ router with the proposed buffer architecture is able to provide almost similar performance using a 50% smaller buffer as compared to the conventional VOQ router.