Abstract

The goal of this study is to verify an innovative system integration technology that integrates the connections beyond the I/Os of the chips. As the signals come out from the IC chip, it passes through UBM, bumps and solders in order to connect to the outside world. But the line density of the substrate underneath the die can't shrink as fast as the Moore's law. Hence the packaging industry developed the interposer (2.5D) on top of the substrate to solve the fine line requirement of substrate. The advanced chip packaging structure includes components of interposer, substrate and PCB. Each connection component needs a core to support during manufacturing process. The final packaging structure uses solders to connect between interposer, substrate and PCB. The solders are left in the final packaging structure. In this paper, a new structure that do not need the cores and most of solders in the final packaging structure is proposed and tested. This new system integration packaging structure is a solder-minimum, TSV-less and core-less structure. A test chip with 10,000 bumps and 50μm pitch has been designed and manufactured to test this new structure. This new substrate structure composed of two portions; thin film fine line and laminated dielectric. The dimensional changes of the new test substrate were under control to be less than 4μm in 10mm range. Further bonding of the test chips to the new substrate was verified using a commercial TCB bonder.

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