An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Abstract

Leakage has become one of the most dominant factors of power consumption and signal integrity of nanometer-scale integrated circuits. Recently, power-gating structures have proven to be effective in controlling leakage. In this paper an alternative dual-V th reduced power-gating structure is proposed for better reduction of leakage currents, especially for low-power and high-performance portable devices. The proposed technique maintains an intermediate power-saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF modes. In addition, an analysis of ground bounce due to power-mode transition in power-gating structures is presented. It is demonstrated that the proposed technique provides a way to control ground bounce during power-mode transition. Due to the presence of the intermediate state, its stepwise turning on feature will provide higher reduction of the magnitudes of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.