An innovative approach of computational fault detection using design for testability of CP-PLL

Abstract

This paper presents an innovative approach to detect computational fault using design for testability (DFT) of CP-PLL (charge pump phase locked loop) to allow simple digital testing. The proposed structure is useful in mixed signal IC (incorporating both analog and digital block on the same chip) testing. With increasing complexity of mixed signal IC the demand of preparing the low cost testing circuitry also gets increased. Here CP-PLL is taken as the mixed signal IC wherein the proposed method uses the charge pump as stimulus generator and the VCO (voltage controlled oscillator) as measuring device for testing the CP-PLL. It avoids the need of interfacing any foreign component and decreases the area overhead of whole IC. Moreover, testing circuitry is applied at the digital part of the CP-PLL i.e. PFD (phase frequency detector) and the analog part i.e. charge pump; loop filter and VCO are controlled by PFD only. Consequently the efficiency of the testing process avoiding the loading effect at analog node is increased. Fault simulation results indicate that the proposed structure posses high fault coverage of 98.2% and less area overhead of about 3.025%.