Abstract
This paper presents a differential inductorless transimpedance amplifier (TIA) design using Global Foundries 0.18-µm CMOS BCDlite technology. The proposed TIA consists of a unique altered-regulated cascode (ARGC) input stage that uses a parallel PMOS and immittance converter (IMC) to lower the input impedance and mitigate the photodiode capacitive loading effects on the TIA bandwidth. It also has a unique three-cascaded gain stages with third-order interleaving differential feedbacks (3G3F) that maintains bandwidth while increasing the TIA gain. The buffer stage consists of a common source amplifier with a source follower to prevent gain drop and to match to 50 Ω, respectively. The proposed TIA (including buffer) has a transimpedance gain of 56.05 dBΩ. The bandwidth is 5.18 GHz and the core dc power consumption is 20.9 mW (total dc power with buffer is 34.6 mW) from a 1.8 V supply.
Published Version
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