An improved reconfiguration algorithm for handling 1-point NoC failures

Abstract

In today’s world, the demands for high-performance computing necessitate faster on-chip communication. Current chips with a large number of on-chip elements need an efficient alternative such as network-on-chip (NoC) for on-chip communication. As technology down scales toward the deep sub-micron, process variability makes the transistors more unreliable. Hence, on-chip elements including NoC can suffer from permanent/transient failures. In an NoC, 1-link/1-router failure can disrupt overall connectivity. The paper presents an improved routing reconfiguration algorithm for handling all 1-point permanent failures in 2D mesh NoC. By 1-point failure, we mean a failure can be occurred on any network link/router. State-of-the-art approaches either require a large number of reconfiguration cycles or provide partial support for 1-point failures, i.e., cover only 1-link failures. Proposed approach performs partial reconfiguration of routing function implemented using logic-bits instead of costly routing tables, thus reducing hardware overheads for larger networks as well. In terms of performance, the average flit latency cycles are reduced up to 31% and the average network throughput is improved up to 14.5% for 1-router failure in 8 × 8 2D mesh NoC. For 2-router failures, the improvements are 20% and 13% in terms of average flit latency cycles and average network throughput, respectively.