An improved mapping method of buffer for line based architecture of 2-D DWT

Abstract

The number of arithmetic units used in the one-dimensional (1D) discrete wavelet transform (DWT) is the main consideration for reducing the area of VLSI implementation of 1D DWT, while the size of intermediate memory used for data buffering is another dominate factor of effecting hardware complexity of VLSI implementation for two-dimensional (2D) DWT. In this paper, we exploit the essential relationship between the size of temporal buffer (TB) required in the line-based architecture for 2D DWT (LBA2DDWT) and the number of registers used in the 1D DWT module, and present an improved method of mapping the registers used in the 1D DWT to the TB required in LBA2DDWT. Comparison results with the other design reported in previous literature demonstrate that, the proposed mapping method can reduce efficiently the size of memory required in LBA2DDWT.