An improved high gain and wide bandwidth operational amplifier for the SHA circuit in a pipelined ADC

Abstract

This paper presents a high gain and wide bandwidth fully differential operational amplifier (op amp) used in a sample and hold amplifier (SHA) circuit for a 12bit, 50Ms/s pipelined ADC. The gain-boosted technique is adopted to achieve a high gain without reduction of the output swing, while a new frequency compensation method is developed to compensate the bandwidth degradation caused by the gain-boosted structure. Simulation results show that the amplifier exhibits a gain of 114dB, unity gain bandwidth of 721MHz, and 2V output range from a single 3.3V supply. A sample and hold circuit employing the amplifier is implemented in a commercial 0.35µm CMOS process, the measurement results show that the amplifier should meet the requirement for the pipelined ADC operating at up to 50MHz sampling clock.