A Novel High-Speed High-Gain and Low-Noise CMOS Amplifier in 0.18µm Process

Abstract

This work describes a novel high-speed, high-gain and low-noise CMOS operational amplifier with interior CMFB for high-speed applications. In the proposed structure, the design employs an auxiliary interior CMFB technique to enhance the effective transconductance and hence achieves high gain and high unity-gain bandwidth (UGB), as well. Meanwhile, all the transistors are biased to operate in sub-threshold region to decrease power consumption. Applying the proposed idea, the AC response of the amplifier shows the 88.42dB Dc gain and Unity-Gain Bandwidth (UGB) of 1.45 GHz and the phase margin of 78.2°, respectively. The output and input referred noise plot gives a peak value of 1.83pV/√Hz and 81nV/√Hz, respectively. It is notable that, the noise analysis has been performed with a 6mV signal applied at the input nodes. To measure the ICMR, the DC transfer characteristic of the proposed amplifier is simulated by setting up the amplifier in a unity-gain, non-inverting configuration with a 1.8V supply. The DC transfer characteristic almost rail-to-rail ICMR, from 421µV to 1.756V, as well. Meanwhile, at the 1.8volts power supply and load capacitance of 1pF, the overall power consumed by instrumentation amplifier is 1.39mW. The layout of the proposed amplifier is designed by using the Cadence Virtuoso, the amplifier core occupies an active area of the only 36.05μm×13.40μm (0.483mm2). The simulation results of the proposed amplifier is performed by HSPICE using the BSIM3 model of a 180nm CMOS technology.