A 0.9V, 3.1–10.6 GHz CMOS LNA with high gain and wideband input match in 90 nm CMOS process

Abstract

In this paper, a high gain and wideband input match CMOS low-noise amplifier (LNA) is presented for the ultra-wide band (UWB) application. The main novelty lies in significant improvement in bandwidth by using the inverter cell at the input node, with a peaking inductor at the gate of NMOS device. Self-forward-body-bias (SFBB) concept is also used within the inverter cell to mitigate the trade-off between input matching and power consumption. In the second stage, self bias resistive feedback circuit with the drain peaking inductor is used to increase the gain as well as output matching. Using a standard 90 nm CMOS process, the proposed LNA exhibits a peak gain of 15.3 dB at 9.4 GHz, while, it consumes 13.5 mW power from a 0.9 V supply voltage. The simulation results show S 11 min ) of 1.21–4.6 dB, output return loss −32 dB 22 1 in the frequency range of 3.1–10.6 GHz. When a two tone test is performed with a frequency spacing of 10 MHz, a highest value of third order input intercept point (IIP3) of −3 dBm is achieved. Its other significant advantages are small group delay variation (±50 ps), and gain variation of ±1.21 dB.