An Improved Fault Simulation Approach Based on Verilog with Application to ISCAS Benchmark Circuits

Abstract

This paper presents an approach to fault simulation in the particular context of ISCAS 85 combinational benchmark circuits based on hardware description language (HDL) specification of their gate level netlists. The approach, exploiting the existing force and release features available in Verilog, builds an effective fault simulator by properly utilizing Verilog syntax with application to fault modeling. The implemented simulator system is able to emulate all of the ISCAS 85 combinational circuits. Experimental results show that access to the source code of HDL simulator or its modification is not a requirement to compute faulty responses from a circuit under test (CUT). The proposed simulator is platform independent, thereby making its utility substantially worthwhile