An Improved ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology

Abstract

Compared to bulk CMOS technology, Silicon-on-Insulator (SOI) CMOS technology has many advantages. However, electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR). Although H gate structure with body-contact can solve the problems of floating body effect and edge leakage, it still affects the conduction uniformity when it is used for ESD protection with even a single-finger of a big width. In order to improve the conduction uniformity, An improved body tied source (BTS) structure is adopted, thus the base voltage of each parasitic bipolar can be well kept at the same voltage through almost the same parasitic body resistance. According to the experimental transmission line pulse generator(TLPG) measured results, BTS gate grounded NMOS(GGNMOS) has a higher second breakdown current than H gate GGNMOS, that is 7.5 mA/μm, and BTS GGNMOS of 200 μm width and 0.8 μm length can obtain a robustness level of 3195 V under positive ESD stress and 2310 V under negative ESD stress.