Abstract
A low jitter CMOS ring oscillator phase-locked loop (PLL) is presented in this paper. An improved voltage controlled oscillator (VCO) frequency control method is applied, and additional charge pump switches are used in the designed PLL. The VCO phase noise is −118.65dBc/Hz at 1 MHz offset from 3.125 GHz carrier, and the PLL total output jitter is 1.16ps at 3.125GHz in GlobalFoundries 0.13µm CMOS technology. The PLL locking time is 8µs and the total power dissipation with IO is 9.3mW.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
