Abstract
This paper investigates the feasibility of a backend design for real-time, multiple-channel processing digital phased array system, particularly for high-performance embedded computing platforms constructed of general purpose digital signal processors. First, we obtained the lab-scale backend performance benchmark from simulating beamforming, pulse compression, and Doppler filtering based on a Micro Telecom Computing Architecture (MTCA) chassis using the Serial RapidIO protocol in backplane communication. Next, a field-scale demonstrator of a multifunctional phased array radar is emulated by using the similar configuration. Interestingly, the performance of a barebones design is compared to that of emerging tools that systematically take advantage of parallelism and multicore capabilities, including the Open Computing Language.
Highlights
To measure the benchmarks of digital phased array radar (PAR) backend system performance, millions of instructions per second are often used as the metric
For the cases that the numbers of range gates is equal to 128 and 256, the beamformer can outperform than in the cases that range gates are 512 and 1024. This variation is caused by the capacity cache misses the happened in the last two cases, in which the digital signal processors (DSPs) core needs to wait for the data to be cached
We present a development model of an efficient and scalable backend system digital PAR based on Field-Programmable-radio frequencies (RF) channels, DSP core, and the Serial Rapid IO (SRIO) backplane
Summary
In [1], we had introduced the real-time phased array radar (PAR) processing based on the Micro. Digital PAR backend systems control the overall system, prepare to transmit waveforms, transform received data for use in a digital processor, and process data for further functions, including real-time calibration, beamforming, and target detection/tracking. Compared with FPGA or full-custom VLSI chips, programmable processing devices, such as digital signal processors (DSPs), offer a high degree of flexibility, which allows designers to implement algorithms in a general purpose language (e.g., C) in backend systems [6]. Detection and tracking functions require processors to be more capable of logic and data manipulation, as well as complex program flow control Such features differ starkly from those required for baseline radar signal processors, in which the size of data involved dominates the throughput of processing [6]. For PAR applications, the optimal solution is a hybrid implementation in hardware dedicated for front-end processing, programmable hardware for backend processing, and a high-performance server for high-level functions
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