An Implementation of real-time phased array radar fundamental functions on DSP-focused, high performance embedded computing platform

Abstract

This paper investigates the feasibility of real-time, multiple channel processing of a digital phased array system backend design, with focus on high-performance embedded computing (HPEC) platforms constructed based on general purpose digital signal processor (DSP). Serial RapidIO (SRIO) is used as inter-chip connection backend protocol to support the inter-core communications and parallelisms. Performance benchmark was obtained based on a SRIO system chassis and emulated configuration similar to a field scale demonstrator of Multi-functional Phased Array Radar (MPAR). An interesting aspect of this work is comparison between “raw and low-level” DSP processing and emerging tools that systematically take advantages of the parallelism and multi-core capability, such as OpenCL and OpenMP. Comparisons with other backend HPEC solutions, such as FPGA and GPU, are also provided through analysis and experiments.