An Implementation of Modified Lightweight Advanced Encryption Standard in FPGA

Abstract

Advanced Encryption Standard (AES) is the standardized block cipher, which is used in various applications. AES is well suited for software and hardware implementation with versions of 128,192,256 key sizes. In hardware implementation AES is advantageous as it is more secure, low cost, and has minimized hardware utilization. Lightweight block ciphers are developed for the efficient implementation in hardware. An approach to design a technique to implement AES as lightweight block cipher is an immediate requirement of the time. An approach, to make AES a lightweight block cipher, is being discussed such that designing the steps of AES such as mix columns, substitute byte in AES is to be implemented in a parallel manner. The latency in this implementation is considered to be less comparing the conventional implementation of AES. The conventional and the new approach are to be simulated in XILINX 14.2 and is being compared in the aspects of area and latency. The design is to be implemented in FPGA.