A Low-cost and High Efficiency Architecture of AES Crypto-engine

Abstract

The growing market of WPAN has led to an increasing demand of security measures and devices for protecting the user data transmitted over the open channels. Advanced encryption standards (AES) is the basic security approach for WPAN. To meet the low cost, low power feature and high security demand of WPAN, a low cost, high efficient AES core is proposed in this paper. To achieve low cost, methods of integration and resource sharing are used in designing a very low-complexity architecture, especially in (inverse) byte substitution ((inv) SubBytes) modules and (inverse) mix column ((inv) MixColumn) modules, etc. Further more, AES Encryptor and Decryptor is integrated into a full functional crypto-engine. This very low-cost and high efficiency AES core of IEEE 802.15.4-2006 is designed and emulated on Xilinx FPGA. Simulation results show that this kind of design can be used in resource critical applications, such as smart card, PDA and mobile phones.