Abstract
Traditional genetic algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The compact genetic algorithm (CGA) is a probability vector based genetic algorithm. The article presents an FPGA implementation of the standard compact genetic algorithm with a few changes to improve search power. A data flow and a block diagram design are shown and described in the paper. Results demonstrate the requirements (logical blocks) needed for implementation, the architecture processing speed and the solving power of the CGA for evolvable hardware.
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