An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration

Abstract

This paper presents a RTL-described sub-GHz IoT transceiver(TRX) in 65nm CMOS with 3.3/4.6mW RX/TX power consumption. Most of the TRX is fully-synthesizable with foundry provided standard cells. The TRX has ring oscillator(RO) based a fractional-N injection-locked(IL-PLL) PLL, a digital frequency shift keying(FSK) transmitter, and a digital-intensive heterodyne receiver with all-digital intermediate frequency(IF) stage. To mitigate the adverse effects of layout uncertainty and process voltage temperature(PVT) variations, extensive digital background calibration is proposed. Enabled by the digital calibration, the RO-based injection-locked PLL achieves 0.8ps jitter and -61dBc reference spur, with 40MHz reference frequency and 1.1mW power consumption. The synthesizable transmitter achieves 0.9% error vector magnitude(EVM) and -41dB adjacent channel power ratio(ACPR) with 21.7% system efficiency at 0dBm output power. The digital intensive receiver achieves -94dBm sensitivity and 36dB adjacent channel rejection(ACR), with 3.3mW power consumption.