Abstract

A new tracking system is under development for operation in the CMS experiment at the High Luminosity LHC. It includes an outer tracker which will construct stubs, built by correlating clusters in two closely spaced sensor layers for the rejection of hits from low transverse momentum tracks, and transmit them off-detector at 40 MHz. If tracker data is to contribute to keeping the Level-1 trigger rate at around 750 kHz under increased luminosity, a crucial component of the upgrade will be the ability to identify tracks with transverse momentum above 3 GeV/c by building tracks out of stubs. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are identified using a projective binning algorithm based on the Hough Transform. A hardware system based on the MP7 MicroTCA processing card has been assembled, demonstrating a realistic slice of the track finder in order to help gauge the performance and requirements for a full system. This paper outlines the system architecture and algorithms employed, highlighting some of the first results from the hardware demonstrator and discusses the prospects and performance of the completed track finder.

Highlights

  • An FPGA based track finder for the L1 trigger of the Compact Muon Solenoid detector (CMS) experiment at the High Luminosity Large Hadron Collider (LHC)

  • To implement the Hough Transform (HT) algorithm, the Hough-space can be subdivided into an array of cells, bounded along the horizontal axis by |q/particle transverse momentum (pT)| < q/pmT in, where pmT in = 3 GeV is used for the results presented in this paper, and along the vertical axis by the range in φT covered by the individual subsector

  • After all tracks have arrived from the Kalman Filter (KF), the inconsistent tracks are read out from R_FIFO, and if one has fitted track parameters corresponding to an HT cell location not yet marked in the Matrix, the track is recovered by forwarding it to the output channel, and marking the corresponding address in the Matrix

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Summary

The High Luminosity Large Hadron Collider

To fully exploit the scientific potential of the Large Hadron Collider (LHC) [1], it is planned to operate the machine at a luminosity up to one order of magnitude higher than obtained with the nominal design. Installation of the High-Luminosity LHC (HL-LHC) upgrade [2] is expected to occur during a 30 month shut-down known as Long Shutdown 3 (LS3), starting around 2024, leading to a peak luminosity of 5–7.5 × 1034 cm−2 s−1, corresponding to an average number of 140–200 proton-proton interactions, named pileup (PU), per 40 MHz bunch crossing. Targeting a total integrated luminosity of 3000 fb−1, the HL-LHC will enable precision Higgs measurements, searches for rare processes that may deviate from Standard Model predictions, and increases in the discovery reach for new particles with low production cross-sections and/or multi-TeV masses

The CMS tracker upgrade
Track finding at the Level-1 trigger
An FPGA based track finding architecture
72 LINKS FROM DTCS
Geometric Processor
Algorithm description
Implementation
The hardware demonstrator slice
Demonstrator results
Track reconstruction efficiency
Track parameter resolution
Data rates
FPGA resource usage
Latency
Flexibility and robustness of the system
Future developments and improvements
Improvements to the Hough transform algorithm
Improvements to the Kalman filter algorithm
Move to the ultrascale platform: from demonstrator to baseline system
FPGA resources
Findings
Conclusions
Full Text
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