Abstract

A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial requirement of this upgrade is to provide the ability to reconstruct all charged particle tracks with transverse momentum above 2–3 GeV within 4 μs so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform, followed by a combinatorial Kalman Filter. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system functionality, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle acceptance at a time, processing events taken at 40 MHz, each with up to an average of 200 superimposed proton-proton interactions, whilst satisfying the latency requirement. The demonstrated track-reconstruction system, the chosen architecture, the achievements to date and future options for such a system will be discussed.

Highlights

  • HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not

  • To implement the Hough Transform (HT) algorithm, the Hough-space can be subdivided into an array of cells, bounded along the horizontal axis by |q/particle transverse momentum (pT)| < q/pmT in, where pmT in = 3 GeV is used for the results presented in this paper, and along the vertical axis by the range in φT covered by the individual subsector

  • After all tracks have arrived from the Kalman Filter (KF), the inconsistent tracks are read out from R_FIFO, and if one has fitted track parameters corresponding to an HT cell location not yet marked in the Matrix, the track is recovered by forwarding it to the output channel, and marking the corresponding address in the Matrix

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Summary

The High Luminosity Large Hadron Collider

To fully exploit the scientific potential of the Large Hadron Collider (LHC) [1], it is planned to operate the machine at a luminosity up to one order of magnitude higher than obtained with the nominal design. Installation of the High-Luminosity LHC (HL-LHC) upgrade [2] is expected to occur during a 30 month shut-down known as Long Shutdown 3 (LS3), starting around 2024, leading to a peak luminosity of 5–7.5 × 1034 cm−2 s−1, corresponding to an average number of 140–200 proton-proton interactions, named pileup (PU), per 40 MHz bunch crossing. Targeting a total integrated luminosity of 3000 fb−1, the HL-LHC will enable precision Higgs measurements, searches for rare processes that may deviate from Standard Model predictions, and increases in the discovery reach for new particles with low production cross-sections and/or multi-TeV masses

The CMS tracker upgrade
Track finding at the Level-1 trigger
An FPGA based track finding architecture
72 LINKS FROM DTCS
Geometric Processor
Algorithm description
Implementation
The hardware demonstrator slice
Demonstrator results
Track reconstruction efficiency
Track parameter resolution
Data rates
FPGA resource usage
Latency
Flexibility and robustness of the system
Future developments and improvements
Improvements to the Hough transform algorithm
Improvements to the Kalman filter algorithm
Move to the ultrascale platform: from demonstrator to baseline system
FPGA resources
Findings
Conclusions
Full Text
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