An FPGA-based Hardware Accelerator of RANSAC Algorithm for Matching of Images Feature Points

Abstract

RANSAC algorithm is a powerful algorithm which is widely used to reject erroneous data in the field of automated image analysis and computer vision. In RANSAC, its iterative property leads to higher computation complexity. Therefore, the hardware implementations of RANSAC that have been proposed consume a large amount of resources. In this paper, an FPGA-based resource-efficient RANSAC hardware accelerator is proposed to eliminate false matches of feature points between two adjacent image frames. The proposed design adopts a single-line systolic array structure causing its lower on-chip resource consumption. It can work along with image feature points detection and matching modules on FPGA. The proposed design is evaluated on a ZYNQ XC7Z045 FPGA at 100MHz clock frequency. Processing 128 matching pairs, only needs 4,718 clock cycles. Experimental results demonstrate that its outstanding capability for screening matching pairs, our design can support real-time video processing.