An experimental study of the BO-MOS dynamic RAM cell

Abstract

A novel structure of a one-transistor dynamic MOS RAM cell is developed for higher integration. The buried-oxide MOS (BO-MOS) RAM cell consists of a planar MOSFET transfer gate and a storage capacitor of buried N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> diffusion. This three-dimensional structure results in a cell size of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6F^{2}</tex> with a minimum feature size <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</tex> and the large capacitance ratio of storage to bit-line which is about 4 times that of a typical commercial 64-kbit RAM cell. The soft-error-immunity cell structure is also taken into account. Static device characteristics of the planar MOSFET transfer gate built on an epitaxial layer and the buried storage capacitance are investigated relating to doses of boron implantation to the channel and substrate. Dynamic WRITE/READ operations are performed with an experimental 4 × 10 cell array implemented with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F = 4</tex> -µm features. The technology offers the possibilities of a high density dynamic MOS RAM with a single poly-Si process.