An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller

Abstract

Field Programmable Gate Arrays (FPGAs) are becoming more popular in various areas. Single Event Upsets (SEUs) are faults caused by a charged particle in the configuration memory of SRAM-based FPGAs. Such a charged particle can cause incorrect behavior in the whole system. This problem becomes greater if such a system operates in an environment with increased radiation (e.g. space applications). Lots of techniques to harden FPGAs against faults exist and new techniques targeted to FPGA are in scope of many researchers. One such technique is called Triple Modular Redundancy (TMR). It is important to evaluate these techniques on a real system with a real FPGA. An evaluation platform based on an artificial fault injection and a functional verification for testing fault tolerance methodologies is introduced in this paper. Parts of our experimental system are hardened by using TMR and its experimental evaluation is one of the main parts of this paper. In this paper, we focus on the TMR fault tolerance method and change the target functional unit, on which the method is applied. This allows us to determine the reliability gain obtained through the hardening of a particular functional unit and allows us to compare the results. We propose experiments with various fault injection strategies (multiple and single faults) and monitor impact of faults on both the electronic and mechanical parts of the experimental system.