Abstract
In recent years, various dual MOS gated thyristor structures have been proposed to improve the three pronged trade-off of forward voltage drop, turn-off time and forward biased safe operating area when compared to single gate devices. The dual gate emitter switched thyristor (DG-EST), with its unique thyristor current partitioning mechanism, has been reported to posses superior characteristics when compared to conventional single gate ESTs. In this paper, a detailed study of the device physics of operation of the DG-EST is presented, supported by two dimensional numerical simulations. Effects of variations in the floating emitter length, lifetime in the drift region and temperature on the forward voltage drop are experimentally observed. An analytical model predicting the maximum controllable current density ( J MCC) of the DG-EST is reported and confirmed through experimental measurements. The DG-EST is found to have a superior trade-off curve of on-state voltage drop versus turn-off time when compared to the conventional emitter switched thyristor (C-EST).
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