Abstract
A new ESD (electrostatic discharge) protection circuit was designed and implemented in commercial BiCMOS. One such ESD unit is adequate for each I/O pin to survive ESD stressing of all modes. This novel ESD circuit features adjustable low-trigger-voltage, symmetric active discharge channels in all directions, fast response, and high ESD performance/area ratio. It passed 14 kV HBM and 15 kV airgap IEC ESD zapping. This compact ESD structure minimizes parasitic effects, which is desired for mixed-signal and RF ICs.
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