An equivalent circuit model of NBTI effect for short-channel P-MOSFET

Abstract

An equivalent circuit model of the negative bias temperature instability (NBTI) effect in 65 nm P-MOSFET is presented in this paper. Based on an existing P-MOSFET model of a 65 nm CMOS foundry PDK (Process Design Kit) and several basic electrical components and arithmetic cells in the EDA (Electronics Design Automation) library, an equivalent circuit model for NBTI degradation has been achieved. The electrical components and arithmetic cells include voltage source, voltage-controlled voltage source, voltage-controlled current source, adder, and multiplier. The equivalent circuit model includes five tunable input parameters: gate width (W), gate length (L), temperature (temp), stress time (t), and process corner (typical/fast/slow). The model takes into account the effects of drain-source, drain-gate, and gate-source voltage stress states. The effect of process corner on NBTI is also considered. The simulation results show that the performance curve of this P-MOSFET equivalent circuit model is consistent with the measured data in some published literature. This equivalent circuit model can be utilized for long-term reliability IC design.