Abstract
A novel circuit sizing technique with improved accuracy and efficiency is proposed to resolve the sizing issues in the analog circuit design. The grey wolf optimization (GWO) algorithm has the total number of iterations divided equally for exploration and exploitation, overlooking the impact of balance between these two phases, aimed for the convergence at a globally optimal solution. An enhanced version of a typical GWO algorithm termed as enhanced grey wolf optimization (EGWO) algorithm is presented with improved exploration ability and is successfully applied in analog circuit design. A set of 23 classical benchmark functions is evaluated and the outcomes are compared with recent state of the art. A conventional two-stage CMOS operational amplifier circuit realized in UMC 180nm CMOS technology is used as a benchmark to validate the efficiency and accuracy of the proposed optimization technique. A statistical study is also conducted over the final solution to investigate the exploration ability of the algorithm proving it to be one of the robust and reliable techniques.
Highlights
With the scaling of the CMOS process, the demand for the integration of both analog and digital circuits on the same die has increased
The aspect ratios of the MOS transistors obtained from the enhanced grey wolf optimization (EGWO) using MATLAB are employed for the circuit-level implementation of operational amplifier in Cadence IC616 using the INTEL core i7 4790 CPU@3.60 GHz with 16 GB RAM
This paper addresses the challenge by introducing an improved algorithm, i.e., the EGWO, considering it to be a step towards the improved performance of automated sizing tools
Summary
With the scaling of the CMOS process, the demand for the integration of both analog and digital circuits on the same die has increased. Though the analog circuitry in an integrated circuit (IC) is less when compared to its digital counterpart, its complexity and nonlinearity makes the design process more challenging. The technology scaling has put more constraints on the analog circuit design, making the design process more complicated, time-consuming, requiring skill, and costly, resulting in increased overall time-to-market [1]. Automation of digital circuits has been successful over the past few decades due to its structured nature and high level of abstraction. A typical circuit design process starts with topology selection followed by circuit level implementation, and its transformation into layout [4]. This paper focuses on the second phase of circuit design, i.e, circuit sizing, considering its significance with the presumption that the designer has decided the appropriate topology of the circuit
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