An Energy-Efficient and Approximate Accelerator Design for Real-Time Canny Edge Detection

Abstract

This paper proposes a dedicated hardware design approach focused on the adoption of state-of-the-art approximate adders (AAs) for the design of CMOS (complementary metal–oxide–semiconductor) Canny edge detection hardware accelerators. The proposed method leverages state-of-the-art AAs in the compute-intensive Gaussian and Gradient filter steps of the Canny edge detection algorithm. The key objectives of our accelerator architecture are: (1) to provide real-time Canny edge operation by proposing an energy-efficient ASIC (application specific integrated circuit) architecture and (2) to further reduce energy consumption when adopting the proposed design-time approach for approximate arithmetic operations. The proposed accelerator architecture considers two methods for the magnitude computation: (1) the square root operator and (2) the absolute operator. All proposed architectures herein developed were described in VHDL and synthesized in a 45 nm digital CMOS ASIC design. Results show that the baseline architecture takes only 0.42 ms to process an 8-bit 512 × 512 pixels image at a maximum VLSI operating frequency of 631 MHz. When considering all the approximate architecture versions and the methods for magnitude computation, the maximum energy reduction achieved is 44.3% when compared to the baseline architecture in an iso-performance analysis. This significant energy reduction is achieved when an average F measure quality metric equal to 0.79 is obtained.