Abstract
Approximate computing represents a powerful technique to reduce energy consumption and computational delay in error-resilient applications, such as multimedia processing, machine learning, and many others. In these contexts, designing efficient digital data-paths is a crucial concern. For this reason, the addition operation has received a great deal of attention. However, most of the approximate adders proposed in the literature are oriented to Application Specific Integrated Circuits (ASICs), and their deployment on different devices, such as Field Programmable Gate Arrays (FPGAs), appears to be unfeasible (or at least ineffective). This paper presents a novel approximate addition technique thought to efficiently exploit the configurable resources available within an FPGA device. The proposed approximation strategy sums the k least significant bits two-by-two by using 4-input Look-up-Tables (LUTs), each performing a precise 2-bit addition with the zeroed carry-in. In comparison with several FPGA-based approximate adders in the existing literature, the novel adder achieves markedly improved error characteristics without compromising either the power consumption or the delay. As an example, when implemented within the Artix-7 xc7a100tcsg324-3 chip, the 32-bit adder designed as proposed here with k = 8 performs as fast as its competitors and reduces the Mean Error Distance (MED) by up to 72% over the state-of-the-art approximate adders, with an energy penalty of just 8% in the worst scenario. The integration of the new approximate adder within a more complex application, such as the 2D digital image filtering, has shown even better results. In such a case, the MED is reduced by up to 97% with respect to the FPGA-based counterparts proposed in the literature.
Highlights
Modern digital electronics design must operate in energy efficient, low-cost, and resource-constrained environments
Circuits Hardware Description Language (VHDL) and parametric constructs, are synthesized and implemented within state-of-the-art Field Programmable Gate Arrays (FPGAs) devices; The logic design has been performed to efficiently exploit the specific resources available in the latest FPGA platforms of major vendors; The hardware implementations of novel approximate adders based on the proposed approach are characterized referring to different operands word-lengths and various levels of approximation; they are compared to several state-of-the-art competitors in terms of both circuit level characteristics and accuracy; The proposed approximate addition logic has been applied to the design of 2D digital image filters and its impact on the overall accuracy and energy consumption has been evaluated
The points labelled as New-Lower-part OR Adder (LOA), NewHOERAA, and New-Approximate Adder-6 (AA6) plot the quality gained by the 2D filter based on the new approximation strategy over those based on the approximate adders LOA [13], Hardware Optimized and Error Reduced Approximate Adder (HOERAA) [17], and AA6 [16] versus the penalty paid in terms of energy
Summary
Modern digital electronics design must operate in energy efficient, low-cost, and resource-constrained environments. Circuits Hardware Description Language (VHDL) and parametric constructs, are synthesized and implemented within state-of-the-art FPGA devices; The logic design has been performed to efficiently exploit the specific resources available in the latest FPGA platforms of major vendors; The hardware implementations of novel approximate adders based on the proposed approach are characterized referring to different operands word-lengths and various levels of approximation; they are compared to several state-of-the-art competitors in terms of both circuit level characteristics and accuracy; The proposed approximate addition logic has been applied to the design of 2D digital image filters and its impact on the overall accuracy and energy consumption has been evaluated.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
