Abstract

An empirical DC to high-frequency equivalent circuit model for heterojunction bipolar transistors (HBTs) is presented in this article. This model takes into account the DC soft-knee effect and bias-dependent extrinsic and intrinsic base-collector capacitances and is built over small-signal model based on the S parameters at multiple bias points on wafer measurement. This modeling methodology is successfully applied to predict DC and small-signal S parameters for an InP/InGaAs HBT. Good agreement is obtained between the simulated and measured results.

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