An electrostatic discharge model for thin‐film transistor fabrication

Abstract

AbstractElectrostatic discharge (ESD) is a significant cause of yield loss in thin‐film transistor (TFT) array manufacturing. TFT arrays are at increased risk relative to other electronic components because the TFTs are unprotected; the array has a large inherent capacitance, and TFT processing includes many chucking and conveyance steps that result in triboelectric charge generation. To reduce or eliminate ESD‐caused fallout, an understanding must be gained of an ESD event's fundamental physics, including the mechanism of charge generation, ESD event physics, and TFT failure modes.An equivalent circuit model has been developed to address the physics of how ESD events occur. The ESD event scenarios modeled with this circuit are as follows: (1) the substrate glass is lifted from the chuck, resulting in a non‐uniform static charge; (2) this charge induces a voltage on the A‐side components; (3) the substrate is lifted, causing a voltage increases; (4) the uneven charge generated results in voltage gradients between TFTs, resulting in an ESD event. This model combines the effects of TFT substrate lifting and charge generation, with a simplified equivalent circuit representing the TFT array. The behavior of this circuit was simulated with a spice model (Electronics Research Laboratory of the University of California, Berkeley, CA, USA.) to characterize the ESD pulse.