An electrostatic analytical modeling of high-k stacked gate-all-around heterojunction tunnel FETs considering the depletion regions

Abstract

This paper deals with the analytical modelling of high-k stacked Gate-All-Around Heterojunction Tunnel Field Effect Transistor (GAA-HJTFET) considering the depletion regions. The surface potential is derived from 2D Poisson’s Equation using the Parabolic Approximation Methodology and the Electric field is obtained by differentiating the surface potential. The drain current is obtained by considering volume of the device, shortest tunnelling path using the Kane’s Model. Due to heterojunction of the SiGe the energy band of the device move downwards to the intrinsic region because of which ION current improves, supress ambipolar behaviour of the device and reduces subthreshold swing. ION-IOFF ratio obtained from the device is 1010. Threshold voltage, transconductance is calculated using drain current equation where the threshold voltage is between 0.7 and 0.8 V and transconductance is 280 µA/mV. The results obtained are validated using ATLAS TCAD Simulation Tool.