Abstract
An elastic pipeline mechanism that is especially suitable for data-driven processors is described. With the elastic pipeline scheme, a large processing rate and a smooth data stream in the pipeline are realized at the same time. Two types of self-timed circuits, which are used for data-transfer control circuits in the elastic pipeline, are proposed. Using different types of transfer control circuits, two loop-shaped elastic pipeline mechanisms have been implemented on test chips and are compared with each other. One of these chips demonstrated that the data throughput in the pipeline was 55 megawords per second and that the critical path within a pipeline stage corresponded to 16 inverter delays. This indicates the possibility of high-performance data-driven processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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