An efficient VLSI architecture for the computation of 1-D discrete wavelet transform

Abstract

This paper presents a new architecture for VLSI implementation of one dimensional discrete wavelet transform (DWT). The architecture uses a single filter for the generation of both DWT coefficients and a scaling function for orthogonal wavelets as opposed to the conventional two filter approach. For subsequent levels, we rely on the fold back architecture principles which interleave the decimated scaling functions back into the filters for the subsequent DWT coefficients. Limited use of memory in the design enables efficient implementation of the DWT computation in VLSI.