Abstract
An efficient organization of configuration is proposed to decrease the size of configuration memory and the time of configuration transmission. Different block ciphers are analysed. And, computing features of algorithms are summarized. Then, the configuration is organized according to the heterogeneous Processing Elements (PEs). It is applied to a coarse-grained reconfigurable architecture (CGRA) which is implemented under TSMC 40nm CMOS technology to compare with similar work. The comparison results show that the configuration capacity decreases with the proposed organization structure. Configuration capacity of the algorithm is reduced by 90.93% to 96.91%.
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