A Hierarchical Context Organization of a Coarse-Grained Reconfigurable Architecture for Block Ciphers

Abstract

A Coarse-Grained Reconfigurable Architecture targeted on block cipher is designed in this paper, which can meet the needs of various cipher supporting in the security applications and enhance the performance of these ciphers. By analyzing the character of the execution and data structure of block ciphers, the hierarchical context organization is adopt. AES and DES are mapped to the architecture and the result shows that the configuration time of them are reduced 42% and 39% respectively. Compared with other similar architectures, the proposed one in this paper has the performance advantage. Introduction According to the development of the network communication, the security of data becomes more and more important. Many cryptographic protocols are proposed to ensure the security. As the foundation of these protocols, ciphers can affect the whole system by performance. The cryptographic protocols often have various ciphers to support, while they also have stringent performance requirement because of the increasing network bandwidth. Take IPSec[1] and SSL[2] for example, AES and DES can be chosen for block data encryption by users, and IPSec protocols in network communications needs to support Gbps throughput. As a general solution, GPP (General Purpose Processor) [3] is widely used for its flexibility rich programmability. However, due to the sequential execution mode, GPP is hardly to meet the increasing requirement on performance, which is driven by the consumer demands. On the other hand, ASIC (Application Specific Intergrade Circuits)[4] can provide the best performance for the specific application, since the data flow and the function unit are optimized specially for the target the application. Meanwhile, these delicate function unit and fixed data paths make it incapable of adapting new requirement of applications or update in cryptographic protocols. New philosophy on design of the architecture is required and reconfigurable architecture (RA)[5] is the satisfactory tradeoff between ASIC and CPU. Computing task can be directly mapped onto the resources of RAs to avoid the software execution overheads. The RAs even have the post fabric flexibility so that it can reconfigure themselves for new application requirement or protocol update after implemented. FPGA (Field Programmable Gate Array) is known as the traditional fine-grained RAs, which are widely used in cipher implementation [6]. However, CGRA (Coarse-grained Reconfigurable Architecture) represents another class of reconfigurable architecture, which replaces the LUT (Look-up Table) in FPGA with coarser computational blocks and simplify the interconnection pattern of FPGA. Many ciphers have been implemented onto CGRAs, such as RCPA/RCBA [7]. However, large amount of the configuration in CGRA becomes the bottleneck of performance. A Coarse-grained Reconfigurable Architecture is designed for block cipher. By analyzing the character of the execution and data structure of block ciphers, the hierarchical context organization is adopt to reduce the configuration time and enhance the performance of block cipher. International Conference on Automation, Mechanical Control and Computational Engineering (AMCCE 2015) © 2015. The authors Published by Atlantis Press 1402 Coarse-Grained Reconfigurable Architecture for Block Cipher Architecture Overview. The Coarse-Grained Architecture for block cipher is shown in Fig.1. It consists of three key modules: a Reconfigurable Computing Array (RCA) to speed up computing-intensive tasks, a Context Controller (CC) to configure the RCA, and a data buffer to store the temporary data during the runtime of the RCA. The RCA will process the computations by mapping and setting the relevant configurations (also called the context), which is managed by the Context Controller. There is also two FIFOs provide a high bandwidth data path for plaintext and cipher text. Figure.1:Overview of the coarse-grained architecture for block cipher Reconfigurable Computing Array(RCA). Figure.2: The executing process of CC Hierarchal Context Organization As shown in Fig.1, all the modules in the RCA can be configured, such as read port, write port, PEs and connections. This means a lot of configuration is needed for the whole architecture [8], and it will increase the time cost to configure the RCA. As it is depicted in Eq.1, the total time(Ttotla), of the RCA can be divvied into two parts, configuration time(Tconf) and calculation time(Tcalc).