Abstract
This work describes a hardware architecture implementation of the morphological associative memories (MAM) using reconfigurable hardware devices such as FPGA (Field Programmable Gates Arrays) and its applications in pattern recognition systems. Both learning and recognition processes of the MAM are implemented by means of a parallel architecture using VHSIC Hardware Description Language, obtaining high speed of processing. The performance of the modeled architecture was evaluated when Morphological Hetero associative Memories (MHM) in both max and min types are used. Our proposal was tested to signal recognitions, for this purpose, it was necessary to implement an acquisition and memory systems.
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