An Efficient Implementation of Arbiter PUF on FPGA for IoT Application

Abstract

Field Programmable Gate Array (FPGA) has become an attractive platform for faster growth of the Internet of Things (IoT). However, like other technologies, FPGA needs resilience against various threats. In addition, the un-monitored environment makes IoT devices more vulnerable. In this context, Physically Unclonable Function (PUF) can provide a low-cost and unique security solution over the costly conventional cryptographic system. Although Arbiter PUF (APUF) is the most suitable PUF variant for IoT, implementing a high-quality APUF on FPGA has been proved to be challenging. To date, programmable delay logic (PDL) is the widely adopted primitive to design APUF on FPGA. However, the implementation of PDL based APUF demands hard-macro feature of CAD tool which limits flexibility of the design. Also, such designs require fine-tuning to achieve PUF characteristics. This paper introduces a new switching structure named path changing switch (PCS) which is easily implementable on FPGA, and this PCS is used here to design APUF instead of the PDL. Further, the directed routing constraint is used to implement an exemplary APUF which possess better flexibility. Also, a new structure of the enable logic and manual routing is used to reduce the delay-bias. Finally, the design has been implemented over 15 different Spartan 3E FPGA boards. Experimental results show that the proposed design outperforms the PDL based APUFs in terms of PUF quality metrics without using additional fine-tuning. Also, the implemented design shows significant tolerance against temperature variations.