An efficient heuristic approach on minimizing the number of feedthrough cells in standard cell placement

Abstract

Standard cell design style has been widely applied for the design automation of VLSI circuits because of the easy implementation of the layout design. Since the aim of most standard cell design systems is to minimize the utilization of chip area, the number of feedthrough cells in a standard cell layout will be further minimized to reduce the layout size. In this paper, first, we model a row assignment problem to minimize the number of feedthrough cells in a standard cell placement. Furthermore, an efficient heuristic approach is proposed to minimize the number of feedthrough cells in standard cell placement. The time complexity of the heuristic approach is further proved to be in O(|E|log|E|) time, where |E| is the number of edges in a separation graph. Finally, two standard cell benchmarks, Primary1 and Primary2, have been tested on the proposed approach for the assignment of different number of rows.