An Efficient Hardware Approach for Approximate Logarithmic Computation

Abstract

In this work, we present a technique that combines piecewise linear interpolation technique with a look-up table-based method in a novel way resulting in a logarithmic converter with higher accuracy. The piecewise linear interpolation function is obtained using a new algorithm, which aids in reducing the interpolation error. The algorithm helps in obtaining an optimized interpolation function which tracks the slope of log[Formula: see text] function more accurately. As a consequence, the size of the look-up table used to correct this interpolation error reduces significantly. Further, precision of the logarithmic converter can be improved by adding additional memory without changing the overall hardware. The method of combining linear interpolation with look-up results in high accuracy with less hardware complexity compared to similar existing techniques. The proposed and existing logarithmic converter designs are synthesized on FPGA and compared for their performance. Results indicate that the proposed approach achieves an improvement of 12% to 22% in memory for accuracies ranging from 10-bit to 20-bit.