Abstract
The full adder circuit is a basic unit in digital arithmetic and logic circuits. In this paper an improved full adder in QCA technology is proposed. This design is considerably declined in terms of cell numbers and area, compared to other full adders and delay is kept at minimum. To design this full adder a different formulation for sum and carry outputs of full adder has been used. The simulation results in QCADesigner software confirm that the presented circuit works well and can be used as a high performance design in QCA technology. Finally, the proposed QCA full adder is used to make three sizes of ripple carry adders (RCA) and acceptable results are achieved.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
