An Efficient Design of 8 * 8 Wallace Tree Multiplier Using 2 and 3-Bit Adders

Abstract

In VLSI, hardware architecture requires the multiplier unit as one of the important parts for arithmetic operation. A multiplier is a major component in many hardware architectures, so various experts are focusing their research in multiplier design to accomplish compact area, delay, and power. Numerous case studies were done for many architectures, in that the increased speed and low area are achieved through a reduction of partial products. One and only of the finest methods is Wallace tree multiplier (WTM). In this research article, Wallace tree 8 * 8 multiplier architecture is proposed, and it produces optimized area and delay. Our work targets structuring and execution of Wallace tree 8 * 8 multiplier utilizing VHDL language. Using limiting quantity of partial products, 2-bit and 3-bit adders are utilized in the 8-bit multiplier. In this work, 8 * 8 Wallace tree multiplier development is inspected and reproduced in XILINX Integrated Software Environment tool. In this 8-bit Wallace tree multiplier circuit, our primary objectives are to diminish the area of multiplier circuit and speed up multiplier routine.