An efficient constant multiplier architecture with error correction codes

Abstract

Filters are extensively used in signal processing and communication systems in uses like channel equalization, noise reduction, radar, audio processing, video processing, biomedical signal processing, and study of commercial and business data. SDR needs reconfigurable FIR filter with animatedlyprogrammable filter coefficient. In FIR filter, the multiplication is done between one specific variable (the input) and several constants (the coefficients) and identified as multiple constant multiplications (MCM). An effectual VHBCSE algorithm for FIR filter is employed for 4 bit in addition to 8 bit common sub-expression elimination.4 bit BCSE is applied perpendicularly across neighboring coefficients of the coefficient matrix in the starting and variable-bit BCSE algorithm horizontally within each coefficient. Key goal of this algorithm are, to decrease the normal switching activity of the multiplier and adder blocks. The next goal is to minimize the power consumption with development in the area power product(APP). In some cases, the reliability of filters is critical, and fault tolerant filter implementations are required. Various techniques to achieve fault tolerance were proposed. In complex systems, it is common that some of the filters function in parallel. The parallel filters can be secured using error correction codes (ECCs). In this technique each filter output remains the same of a bit in a traditional ECC. This novel scheme allows additional efficient security when the amount of parallel filters remainsenormous.