An efficient architecture of modified booth multiplier using hybrid adder

Abstract

With the advancement in technology, low power and fast processing have become an essential part for fast growing processors of microsystems. Multipliers are key components in modern designs of System-on-chip processors for high clock frequency, so the performance of multiplier unit really matters a lot. This research presents a new architecture for 8-bit Radix4 modified Booth multiplier with low power and delay operating at 500 MHz frequency. In this proposed architecture, a new encoder for first partial product array is proposed that reduces the first partial product array circuitry to only 5-bit MUX 3:1 having smaller number of components than other state of art architectures having 5-bit MUX 4:1. A modified two's complement method has been proposed for binary inputs having LSB=0 and LSB=1, and separate circuits are made for both the cases which have the low critical paths. Low power efficient GDI and CMOS logic-based SQRT Carry Select Hybrid adders are proposed having full output swing for 8-bit product using proposed 6-bit SQRT CS- Hybrid adders' architecture. Proposed designs are synthesized in Cadence Virtuoso 90nm process technology in which all the circuits are simulated and as a result, power, delay and power delay product come out to be 0.36ns, 201.3µW and 72.468 FJ respectively. The proposed designs provide almost full output swing at 500Mhz frequency.